Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a vertical gate and a method for manufacturing the same.
As the integration degree of a semiconductor device is increased, a channel length of a transistor is gradually decreased. However, the reduction in channel length of the transistor encounters a drain induced barrier lowering (DIBL) phenomenon, a hot carrier effect, and a short channel effect such as punch-through. In order to solve such problems, a variety of methods are being intensively researched by many developers and companies. For example, the methods include a method for reducing a depth of a junction region, a method for relatively increasing a channel length by forming a recess in a channel region of a transistor, and the like.
However, as the integration density of a semiconductor memory device (especially, dynamic random access memory (DRAM)) has come close to gigabits, it is necessary to manufacture a smaller-sized transistor. In other words, the giga-bit semiconductor device requires a DRAM transistor having a device area of less than 8F2, F representing a minimum feature size and even having a device area of about 4F2. Therefore, in the case of a planer transistor in which a gate electrode is formed over a semiconductor substrate and a junction region is formed at both sides of the gate electrode, it is difficult to satisfy the above device area. In order to solve the above-mentioned problems, a vertical channel transistor has been recently proposed.
In accordance with the vertical channel transistor, a buried bit line is formed, and a pillar pattern for forming a vertical gate is then formed. When the pillar pattern is formed, other materials (e.g., a nitride film, an oxide film, etc.) should be etched. In this case, there arises a skirt phenomenon in which a nitride film formed on a back side of the pillar pattern is not sufficiently etched.